1. Field of the Invention
The present invention relates to a phase comparator, and more particularly to a phase comparator included in a clock generating circuit for generating an internal clock signal in synchronization with an external clock signal in a synchronous semiconductor memory device for sending and receiving data in synchronization with the external clock signal.
2. Description of the Background Art
In recent years, systems have been increased in speed. A dynamic random access memory (DRAM) as a main memory has also been speeded with the introduction of a synchronous dynamic random access memory (hereinafter, referred to as an SDRAM) that operates in synchronization with a system clock.
To satisfy data rate demanded by systems, however, the DRAMs as well as microprocessor units (MPU) are required to operate even more rapidly. When sending and receiving data at high speed, windows for the data (i.e., time width in which data are to be transmitted on a bus) are extremely narrowed. Thus, it is necessary to synchronize an external clock signal and an internal clock signal without error such that data are input/output with accurate timing.
For synchronizing clock signals, a delay locked loop (DLL) circuit, for example, is used to generate an internal clock signal based on an external clock signal. In the DLL circuit, a phase comparator should be provided for comparing phases of the external clock signal and the generated internal clock signal so as to successfully generate the internal clock signal in phase-synchronization with the external clock signal.
According to a conventional phase comparator, however, precision in phase comparison is limited due to switching time of a transistor being its component element, inversion time of a latch, difference in load capacitance, and so on. Such limit in detection of the phase comparator has made difficult to dramatically improve the precision of phase comparator.
Thus, in an SDRAM incorporating an internal clock generating circuit having such phase comparator therein, high-speed operation cannot be realized with increased clock frequency.